While using the ADC CH0 structure, I noticed an offset error in the ADC_t structure that defines where CH0 is positioned.
The following is the example of what I see:/ Analog-to-Digital Converter /
typedef struct ADC_struct
{
register8_t CTRLA; / Control Register A /
register8_t CTRLB; / Control Register B /
register8_t REFCTRL; / Reference Control /
register8_t EVCTRL; / Event Control /
register8_t PRESCALER; / Clock Prescaler /
register8_t CALCTRL; / Calibration Control Register /
register8_t INTFLAGS; / Interrupt Flags /
register8_t reserved_0x07;
register8_t reserved_0x08;
register8_t reserved_0x09;
register8_t reserved_0x0A;
register8_t reserved_0x0B;
_WORDREGISTER(CAL); / Calibration Value /
register8_t reserved_0x0E;
register8_t reserved_0x0F;
_WORDREGISTER(CH0RES); / Channel 0 Result /
_WORDREGISTER(CMP); / Compare Value /
register8_t reserved_0x1A;
register8_t reserved_0x1B;
register8_t reserved_0x1C;
register8_t reserved_0x1D;
register8_t reserved_0x1E;
register8_t reserved_0x1F;
ADC_CH_t CH0; / ADC Channel 0 /
} ADC_t;
Fri 30 Jul 2010 07:35:43 PM CEST
While using the ADC CH0 structure, I noticed an offset error in the ADC_t structure that defines where CH0 is positioned. The following is the example of what I see:/ Analog-to-Digital Converter / typedef struct ADC_struct { register8_t CTRLA; / Control Register A / register8_t CTRLB; / Control Register B / register8_t REFCTRL; / Reference Control / register8_t EVCTRL; / Event Control / register8_t PRESCALER; / Clock Prescaler / register8_t CALCTRL; / Calibration Control Register / register8_t INTFLAGS; / Interrupt Flags / register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); / Calibration Value / register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); / Channel 0 Result / _WORDREGISTER(CMP); / Compare Value / register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; / ADC Channel 0 / } ADC_t;
and this is the temporary fix I tried:
/ Analog-to-Digital Converter / typedef struct ADC_struct { register8_t CTRLA; / Control Register A / register8_t CTRLB; / Control Register B / register8_t REFCTRL; / Reference Control / register8_t EVCTRL; / Event Control / register8_t PRESCALER; / Clock Prescaler / register8_t CALCTRL; / Calibration Control Register / register8_t INTFLAGS; / Interrupt Flags / register8_t reserved_0x07; register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; register8_t reserved_0x0B; _WORDREGISTER(CAL); / Calibration Value / register8_t reserved_0x0E; register8_t reserved_0x0F; _WORDREGISTER(CH0RES); / Channel 0 Result / register8_t reserved_0x01; register8_t reserved_0x02; register8_t reserved_0x03; register8_t reserved_0x04; register8_t reserved_0x05; register8_t reserved_0x06; _WORDREGISTER(CMP); / Compare Value / register8_t reserved_0x1A; register8_t reserved_0x1B; register8_t reserved_0x1C; register8_t reserved_0x1D; register8_t reserved_0x1E; register8_t reserved_0x1F; ADC_CH_t CH0; / ADC Channel 0 / } ADC_t;
It looks like this is due to the removal of other channels in other Xmega devices (CH1, CH2, CH3).
This could apply to other D3 device files.
Thanks Mike
This issue was migrated from https://savannah.nongnu.org/bugs/?30604