How to use sdk to debug after finishing the IP Integration flow

[tangyuelm]

Any issues related to HDK or SDK should be filed on FPGA development Forum.

The AWS FPGA Development User Forum is the first place to go to post questions, suggestions and important announcements. Hello, I just successfully ran the cl_ipi_cdma_test example for the IP Integration flow. However, I have no idea how to use sdk to debug rather than using the sudo ./test_cl because sdk can help me generate BSP. I searched for the tutorial of sdk but it says that the FPGA binary file is required. However, for the IP integration flow, it cannot generate bitstream but a checkpoint. Is there any way to debug with sdk with the generated checkpoint?

[AWSbatsunil]

Hi tangyuelm,

I am extremely sorry for replying late.

The SDK contains the runtime environment required to run on EC2 FPGA instances. Please refer to Runtime Tools (SDK).

After the Implementation Step, one should move to AFI Creation step.

Let us know if you need more information.

Thanks, Sunil.

[tangyuelm]

Thanks for your reply. I have already created AFI and it can run successfully when I use the referenced .c code. However, I want to know how to use sdk GUI to debug after I loaded the image. I have not found more instructions about that. Could you provide more information?

Best Wishes, Yue

[tangyuelm]

Up to now, I can only find ways to run the image by the CMake file. However, Is there any way to run the image in sdk GUI by the flow of creating project application -- generating BSP -- build -- run?

[AWSbatsunil]

Hi tangyuelm,

The SDK is a set of software tools to manage the AFIs that are loaded on the FPGA instance. It doesn't provide a GUI. If you want to debug the software application that you have written you need to add/check the logs that are needed for the application. The SDK tools provides utilities to check the state of the FPGA. If you want to debug your hardware logic you have to follow this link.

Let us know if you need more information.

Thanks, Sunil.

[AWSbatsunil]

@tangyuelm ,

Let us know if you need any more information. If it solved the purpose we can close this issue.

Thanks, Sunil.

[tangyuelm]

Hi Sunil,

I see the link, but I still cannot figure out how to run the FPGA program with the SDK application project on AWS. Besides, we also write the main function in the SDK application project using c++ instead of c. Are there any specific tutorials?

Best Wishes, Yue

[tangyuelm]

If I want to create my own HLS IP and use several separate DMAs to transmit data between DDR and on-chip buffer, except the XDMA, can I just use the SDK application project to control the Mocroblaze processor? I saw the XDMA driver has some APIs to send burst data, but how can it both control my IP using AXI and send AXI streams via DMA together? In our previous design, the SDK application project can achieve it easily with BSP, so I am wondering whether the SDK application project with the BSP is still supported in AWS? Besides, can I use four separate DMA channels with separate ports to one DDR, or the Microblaze processor only supports one central DMA?

[deeppat]

Hi @tangyuelm , sorry for the delayed response. We are working with Xilinx on getting a response to you as soon as we can.

[deeppat]

Hi @tangyuelm,

For controlling the Microblaze using SDK I got the following guidance from Xilinx:

• Add MDM into the microblaze and use the XVC to connect to it for debug. use "EXTERNAL HIDDEN" for bscan
• Export to SDK after IPI (User can generate BSP/SDK project using this)
• Continue to generate AFI as normal
• Load AFI as normal on an F1 instance
• Connect virtual JTAG XVC (https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md)
• Connect to Virtual cable as you would a normal JTAG and connect to the Microblaze MDM and download elf.

Could you give this a try and see if that works for you?

-Deep

[tangyuelm]

Hi Deep,

Thanks for your attention. I will have a try.

Best Wishes, Yue

[deeppat]

Thanks @tangyuelm. Closing this issue.