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Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
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AXI "bvalid" behavior and latency #556

Closed useragdp1 closed 2 years ago

useragdp1 commented 2 years ago

  1. When is BVALID returned? a. Is it after write to DDR has been sent? b, Is it after write to PCIe bus from FPGA or ack from host?

  2. What is the latency from WLAST assertion to BVALID assertion on both DDR and PCIM interfaces? If it's variable, what is the range?

  3. For PCIM interface a. After receiving BVALID for write to address Z, are subsequent reads to Z guaranteed to respond with previous write to Z. b. If SH-PCIM accepts write to address A followed by write to address B, will the host memory be written in the same order? c. If the answer to above question is NO, then, if CL waits for BVALID for address A and then writes to address B, will the host memory now guaranteed to write A and then write B.

czfpga commented 2 years ago

Hi useragdp1,

I would recommend you run the cl_dram_dma example simulation and check out the waveforms of the particular interface you're interested. In general, we don't specify this type of latency as it has too many dependencies on traffic, memory state, targeted address space, etc,.

For the ordering questions on PCIM, I would recommend you refer to AMBA AXI protocol for the write and read ordering. The PCIM is compliant to the AXI4 protocol with a few limitations.

Thanks,

czfpga commented 2 years ago

Hi useragdp1,

Is there any other questions you have? If not, I'll go ahead resolve this issue. Please feel free to open a new one for any new questions you might have in future. Thanks.

kyyalama2 commented 2 years ago

Assuming resolved. Please feel free to re-open if you need further help