Closed wirthjohannes closed 2 years ago
Hi @wirthjohannes,
Thank you for reaching out on this issue. Somehow I met trouble recreating this issue using using FPGA Developer AMI v1.12.1 (HDK version 1.4.24) with Vivado 2021.2
Here are the last a few lines I got by following this : https://github.com/aws/aws-fpga/tree/master/hdk/cl/examples/cl_hello_world_ref_hlx#create-example-design-command-line
[Thu Jun 23 21:12:02 2022] Launched impl_1...
Run output will be captured here: /home/centos/aws-fpga/hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/example_projects/cl_hello_world_ref.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 3687.641 ; gain = 0.000 ; free physical = 56931 ; free virtual = 70894
[Thu Jun 23 21:12:02 2022] Waiting for impl_1 to finish...
[Thu Jun 23 21:16:55 2022] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'synth_1'
wait_on_runs: Time (s): cpu = 00:04:45 ; elapsed = 00:04:53 . Memory (MB): peak = 3687.641 ; gain = 0.000 ; free physical = 56862 ; free virtual = 70895
INFO: [Common 17-206] Exiting Vivado at Thu Jun 23 21:16:55 2022...
Can you please try cloning down the project repo to a new location and rerun the example from scratch to see if you still see the problem? If so, can you please share the build log so I can check through it to see if I can recreate the issue on my end.
Thanks,
Chen
Hi Chen,
yes, I also get this output from the build script. The third to last line in the output you posted states that the run "synth_1" has failed, but there is no information about the actual error.
So I looked further and opened the Vivado project in cl_hello_world_ref_hlx/build/scripts/example_projects/
with the Vivado GUI.
There I found the error messsage from my original post in the Log-Tab under "synth_1". Alternatively the same output with the error message can also be found in cl_hello_world_ref_hlx/build/scripts/example_projects/cl_hello_world_ref.runs/synth_1/runme.log
.
Thank you for the help Johannes
Hi Johannes,
Thank you, I now see the same error message from runme.log
file. Let me check that property setting Tcl command you pointed out with the team. I'll keep you posted as soon as I have a conclusion.
Thanks again.
Chen
Hi Johannes,
We've reviewed that Tcl script. The command on line 90 is indeed unnecessary due to a latest tool update in Vivado. Thank you for bringing this up. We'll apply a fix shortly. I'll let you know once the it's released.
Thanks,
Chen
Hi, I'm using Vivado 2021.2 and I have temporarily commented this line (line 90) out. However platform_verify fails when generating the AFI. I'm not sure if this is the cause. My design is built against the provided AWS shell and meets timing.
Hi @Quarky93,
Thank you for contacting us. I see you've opened a new issue. Let's use that to discuss the questions you have.
Thanks,
Chen
Hello,
I tried to build the example design
cl_hello_world_ref_hlx
using the information provided here: https://github.com/aws/aws-fpga/tree/master/hdk/cl/examples/cl_hello_world_ref_hlx#create-example-design-command-lineWhen using older versions of Vivado (e.g. Vivado 2019.2 with aws-fpga 1.4.13) this works fine. However with Vivado 2021.2 and aws-fpga 1.4.24 this fails at the the end of the synthesis:
The issue seems to be this line: https://github.com/aws/aws-fpga/blob/master/hdk/common/shell_v04261818/hlx/build/scripts/subscripts/make_post_synth_dcp.tcl#L90. If I just remove this line from the script, the run completes successfully.
However I'm unsure if removing this line might have some unintended side effects, and if so, what a better solution would look like. Do you have some more information about this?
Thanks in advance