Closed vsoBen closed 1 year ago
Hello,
Thank you for opening an issue and proposing these changes! You can also open up a pull request within GitHub to introduce these changes. We'd greatly appreciate more information on how to reproduce this simulation failure.
cl_sh_ddr_awuser
& cl_sh_ddr_aruser
) in cl_ports_sh_bfm.vh
?
Thanks again! -Joe
closing the thread since no recent activity. Please feel free to reopen if further help is needed. Thanks
fpga.sv is using module sh_bfm with inputs cl_sh_ddr_awuser and cl_sh_ddr_aruser.
These inputs shall be added in cl_ports_sh_bfm.vh
diff --git a/hdk/common/shell_v04182104/hlx/verif/cl_ports_sh_bfm.vh b/hdk/common/shell_v04182104/hlx/verif/cl_ports_sh_bfm.vh index a3ab4b8..9c71d75 100755 --- a/hdk/common/shell_v04182104/hlx/verif/cl_ports_sh_bfm.vh +++ b/hdk/common/shell_v04182104/hlx/verif/cl_ports_sh_bfm.vh @@ -190,6 +190,9 @@ input logic [31:0] ddr_sh_stat_rdata1, input logic [7:0] ddr_sh_stat_int1,
output logic [7:0] sh_ddr_stat_addr2, output logic sh_ddr_stat_wr2, output logic sh_ddr_stat_rd2,