Implement post-PAR timing analysis

azonenberg / openfpga

Open FPGA tools

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Implement post-PAR timing analysis #39

Open azonenberg opened 8 years ago

azonenberg commented 8 years ago

Static is preferred, topological would be OK probably. Needs timing data that is not currently released by Silego. Will need to characterize or get them to publish it.

ArcaneNibble commented 7 years ago

[ ] ``` [Blinky] has a stateful feedback loop in a fabric-based (vs hard IP) counter but my timing analyzer thinks everything is combinatorial right now it tries to trace D to Q combinatorially```