badeaa3
commented
2 months ago Goal 1
Lots of confusion about merging in the firmware.
Summary:
- create a new repo because this firmware is not common blocks. Done: https://github.com/Fermilab-Microelectronics/cms_pix_28_test_firmware. Then add the spacely-caribou-common-blocks as a submodule
- remove all branches from the spacely-caribou-common-blocks
Comments:
- the repo now works with submodule https://github.com/Fermilab-Microelectronics/cms_pix_28_test_firmware
- git clone git@github.com:Fermilab-Microelectronics/cms_pix_28_test_firmware.git --recursive
- now it needs to be updated to point to submodules/spacely-caribou-common-blocks/ for the axilite and other common blocks
- add in the peary device and memory map text file to the repo
- delete the dev branches in the spacely-caribou-common-blocks
Successfully recursive cloned the new repo and generated bitstream, then test spacely.
[abadea@fasic-137645 PySpacely] python Spacely.py
----------------------------------------------------------------------------
|(WARNING) You do not have one or more modules required by Glue Converter: |
|No module named 'bokeh' |
|To use Glue Converter functions you may need to re-run SetupWindows.ps1, |
|or install the required modules manually. |
----------------------------------------------------------------------------
* * * TARGETING "CMSPIX28" ASIC * * *
+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+
+ Welcome to Spacely! +
+ Let's do some science together. +
+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+*+
Did you know you can skip interactive initialization with --defaults ?
<DBG> <2024-06-25 16:46:00> INSTR lint check completed successfully.
<INF> <2024-06-25 16:46:00> spacely-asic-config/CMSPIX28/CMSPIX28_Routines.py specifies 1 instruments that need to be initialized: ['car']
<INF> <2024-06-25 16:46:00> V_SEQUENCE not defined in Config. No Vsources will be initialized.
<INF> <2024-06-25 16:46:00> I_SEQUENCE not defined in Config. No Isources will be initialized.
<DBG> <2024-06-25 16:46:00> HAL init skipped
<DBG> <2024-06-25 16:46:00> NI init skipped
DEFAULT: Initialize 1 Test Instruments. 'n' to Skip>>>
<DBG> <2024-06-25 16:46:00> ~ ~ Configuring CaR board ~ ~
<DBG> <2024-06-25 16:46:00> [Step 1] Setting PCA9539 Dir to Output
<DBG> <2024-06-25 16:46:00> ~ ~ Done Configuring CaR board ~ ~
<NOTI> <2024-06-25 16:46:00> Caribou car successfully initialized!
<DBG> <2024-06-25 16:46:00> NI INSTR init
<NOTI> <2024-06-25 16:46:00> NI PXI initialized
ERROR: V_WARN_VOLTAGE not defined in ASIC config file.
No automatic voltage checking will be performed.
# Spacely ready to take commands (see "help" for details)
> ~r3
<DBG> <2024-06-25 16:46:02> Evaluating: ROUTINE_test_loopback_CFG_STATIC()
Starting register value sw_write32_0 = 0
Write to sw_write32_0: True. Wrote 570425343 and register reads 570425343. hex_list = ["4'h2", "4'h1", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Sending OP_CODES: 4'h2, 4'h3
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 570425610 and register reads 570425610. hex_list = ["4'h2", "4'h2", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
Write to sw_write32_0: True. Wrote 587202826 and register reads 587202826. hex_list = ["4'h2", "4'h3", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
sw_read32_0 = 266
sw_read32_1 = 6
Expected in sw_read32_0 ["11'h0", "1'h0", "1'h0", "5'h4", "6'ha"] 266
Starting register value sw_write32_0 = 587202826
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
sw_read32_0 = 0
sw_read32_1 = 0
Sending OP_CODES: 4'h4, 4'h5
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 603980042 and register reads 603980042. hex_list = ["4'h2", "4'h4", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
Write to sw_write32_0: True. Wrote 620757258 and register reads 620757258. hex_list = ["4'h2", "4'h5", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
sw_read32_0 = 266
sw_read32_1 = 24
Expected in sw_read32_0 ["11'h0", "1'h0", "1'h0", "5'h4", "6'ha"] 266
Starting register value sw_write32_0 = 620757258
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
sw_read32_0 = 0
sw_read32_1 = 0
<INF> <2024-06-25 16:46:11> This Routine took: 0:00:09In 1 week if there are no new problems then we delete the dev branches in the common blocks repo. I set a reminder for June 2nd.
Goals: