08/06/24

[bparpillon]

Goal:

• [x] 1. Flash FPGA with cd_ip1_test2
• [x] 2. Test routine 12 with new FW - scanLoad should fire after 5188x2 cycles
• [x] 3. Restructure routine 12 so that we can program the DNN, the Pixels and the hidden registers
• [ ] 4. Add a smog test to routine 12

[bparpillon]

We observe config_out = config_in after 5164 clock cycle as expected since the hidden registers are not connected to config_out.

The first 5188 cycles are observable To write to the first 5188 registers: We need to write to the entire address space for array_0[0:255] ->256 addresses of 16 bit = 4096 bits We need to write to a section of array_1[0:67] = 1088 bits We need to write to the 4-bit MSB of array_1[68] to complete the final 4 bits 4096+1088+4 = 5188

The second set of 5188 cycles in not as it is getting stored directly inside the ASIC registers. To write to the second 5188 registers: We need to write to the 12-bit LSB of array_1[68] = 12 bit We need to write to the entire address space left of array_1[69:255] = 3004 bits We need to write to array_2[0:134] = 2160 bits we need to write to the 12-bit MSB of array_2[135] = 12 bit 12+3004+2160+12 = 5188