Open zaporozhets opened 3 years ago
Hi,
First of all, thanks for awesome tools.
I noticed that write_project_tcl_git adds BD's Verilog references with full path. For example:
write_project_tcl_git
# Adding sources referenced in BDs, if not already added if { [get_files dbg_bridge.v] == "" } { import_files -quiet -fileset sources_1 /home/taras/dev/yo/external/core_dbg_bridge/src_v/dbg_bridge.v } if { [get_files dbg_bridge_fifo.v] == "" } { import_files -quiet -fileset sources_1 /home/taras/dev/yo/external/core_dbg_bridge/src_v/dbg_bridge_fifo.v } if { [get_files dbg_bridge_uart.v] == "" } { import_files -quiet -fileset sources_1 /home/taras/dev/yo/external/core_dbg_bridge/src_v/dbg_bridge_uart.v } if { [get_files dbg_bridge_wrapper.v] == "" } { import_files -quiet -fileset sources_1 /home/taras/dev/yo/fpga/common/rtl/dbg_bridge_wrapper.v }
So I made a tiny to add_references in write_project_tcl_git.tcl and it does the following:
add_references
write_project_tcl_git.tcl
# Adding sources referenced in BDs, if not already added if { [get_files dbg_bridge.v] == "" } { import_files -quiet -fileset sources_1 ../../../external/core_dbg_bridge/src_v/dbg_bridge.v } if { [get_files dbg_bridge_fifo.v] == "" } { import_files -quiet -fileset sources_1 ../../../external/core_dbg_bridge/src_v/dbg_bridge_fifo.v } if { [get_files dbg_bridge_uart.v] == "" } { import_files -quiet -fileset sources_1 ../../../external/core_dbg_bridge/src_v/dbg_bridge_uart.v } if { [get_files dbg_bridge_wrapper.v] == "" } { import_files -quiet -fileset sources_1 ../../common/rtl/dbg_bridge_wrapper.v }
What do you think? Can we merge it?
Cheers, Taras.
Hi,
First of all, thanks for awesome tools.
I noticed that
write_project_tcl_git
adds BD's Verilog references with full path. For example:So I made a tiny to
add_references
inwrite_project_tcl_git.tcl
and it does the following:What do you think? Can we merge it?
Cheers, Taras.