vgurevich
commented
2 years ago Like all the other high-speed systems with multiple pipes, Tofino does not maintain coherency between stateful objects in different pipes -- that would be prohibitively expensive. The application needs to be aware of that.
For a variety of technical reasons, Tofino compiler does not support automatic splitting of indirect objects across multiple stages. However, it is very easy to do on your own: you can create multiple individual instances and decode a wide index in your code. We do provide an example of this approach in Intel Connectivity Academy classes.
The specific scaling information has nothing to do with the architecture per se and should not be discussed in the open forum. However, you can always ask this question in the appropriate Intel support forum.
In the, "Identical P4 code for all pipes " section the specs say, identical code is executed on all the pipes? Now if the P4 code contains access to register-based stateful memory, does Tofino maintains coherency among the register values across the pipes?
Can an Indirect Register array spread across over multiple stages? I am mainly interested to know how many flowlet information I can maintain in a register array. Is this number bounded by the SRAM available in each stage?