Loopy's new wave of FDS RE:
-- https://forums.nesdev.com/viewtopic.php?p=232662#p232662
-- Sweep test its lowpass filter
-- Waveform DAC nonlinearity model? (Maybe just a slider from 0 perfect to 1 = big discontinuity... a harmonic recursion that remaps the ranges to 0-255 with overlap?)
-- FDS verify all halts / non-halts
N163 what happens when you cut down a very long period with a short one (does it take multiple ticks to drop down phase? can probably read it back to test?)
2A03 verify all halts / non-halts (should be well documented by now, MMC5 should be same)
N163 verify all halts / non-halts
VRC6 verify all halts / non-halts
5B / VRC7 halts should be known now
Conflict between $E000 silence of N163/VRC7 with 5B multichip? (Block these in multichip. Only N163 actually implements it currently.)
VRC7 test register, VRC7 $E000 register.
APU square period should be 8 not 16 long and instead internal period register should be doubled to simulate 1/2 clock divider.
Triangle "silence on 0" seems to reveal inconsistent halting behaviour, may also affect init option? (Does triangle init explicitly init to phase 0 correctly?)
The following is a list of planned changes I want to finish before the stable release of 2.5: