Missing the file for h264topsim.vhd

bcattle / hardh264

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

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Missing the file for h264topsim.vhd #1

Open Rohi1710 opened 8 years ago

Rohi1710 commented 8 years ago

sample_int.yuv file is missing

SNThunderbolt commented 7 years ago

Hello your codes are quite impressive... I was wondering if you have the "sample_int.yuv"?

hamayounahmad commented 6 years ago

Kindly share "sample_int.yuv" or email me hamayounahmad@gmail.com Many thanks

ingenieriaam commented 4 years ago

https://github.com/QUSIR/x264_demo/blob/master/test/sample_int.yuv This project contains the file. With this file, I was able to run the test bench.

gbieszczad commented 2 years ago

you can create your own files with ffmpeg or check the one I have made for my bench https://github.com/gbieszczad/hardh264