A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
I have read all files of your work.THANKS,it could use in simulink.But When I add to the project in altera meachine.I have some problems.1.the date from camera is yuv format,we write it into fifo stream to sdram and read fifo stream from sdram to your work to encode to h264 format. Then we used the output stream to Network card or serial port to computer to appear the vedio. 2.But when I see your h264topsim.vhd ,it read datas and Arrange into matrices.when datas in intra4*4_DATAI,it was arranged into materices.Should i use another sdram to arrange the datas from camera?THANK for ANSWER.
I have read all files of your work.THANKS,it could use in simulink.But When I add to the project in altera meachine.I have some problems.1.the date from camera is yuv format,we write it into fifo stream to sdram and read fifo stream from sdram to your work to encode to h264 format. Then we used the output stream to Network card or serial port to computer to appear the vedio. 2.But when I see your h264topsim.vhd ,it read datas and Arrange into matrices.when datas in intra4*4_DATAI,it was arranged into materices.Should i use another sdram to arrange the datas from camera?THANK for ANSWER.