A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
Hi, I'm trying to implement your IP core into fpga but I'm confused by all the inputs. Does anyone have an example for operating
with an IP core? Thank you.
Hi, I'm trying to implement your IP core into fpga but I'm confused by all the inputs. Does anyone have an example for operating with an IP core? Thank you.