testbench with higher resolution input video - Githubissues

bcattle / hardh264

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

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testbench with higher resolution input video #9

Closed swleungbrian closed 1 year ago

swleungbrian commented 1 year ago

Dear Sir, I am trying to run simulation with input yuv at higher resolution (1080p ) and errors popped up and halted simulation like below: Looking forward to your kind advice on this.

110981 bytes in NAL (28:1 compression) using QP: 28 Framenum: 2 read in ok. Using QP: 28 Warning: VALIDI has fallen when in middle of block Time: 68083005 ns Iteration: 1 Process: /h264top/xbuffer/line131 File: C:/Users/swleung/brian/workspace/verilog/4ev/20221005_1737_h264_vhdl/h264_vhdl/h264_vhdl.srcs/sources_1/imports/src/h264buffer.vhd ERROR: Index 540 out of bound 0 to 539 Time: 68085405 ns Iteration: 1 Process: /h264top/line1170 File: C:/Users/swleung/brian/workspace/verilog/4ev/20221005_1737_h264_vhdl/h264_vhdl/h264_vhdl.srcs/sim_1/imports/tests/h264topsim.vhd

Regards,

Brian

swleungbrian commented 1 year ago

Hi all,

I found that it's problem with 1080p resolution. 1080 is not a integer multiple of 16 and will have problems with the existing code. It was fine if i test it with 720p or even 2560x1600 (modified hd in module generating test.264).

Thanks,

Brian