Add VU macro instructions

[chaoticgd]

I've added all the VU macro mode instructions, mostly implemented as pcodeop stubs. It may be beneficial to implement some of these in the future, but for the purposes of this PR I'm mainly concerned with getting an accurate disassembly.

Instructions shared between macro mode and micro mode have been put in a new file called vuupper.sinc with the intention that this file can be reused if support for micro mode code is added in the future.

It's not entirely finished and there are still some instances where the disassembly differs from that of PCSX2. If you find any of these yourself, it would be helpful to post the bytes of the instruction causing the issue.

Feedback welcome.

[beardypig]

Awesome. This is a really good contribution :)

[astrelsky]

Sweet. I know there are some sleigh processors which have vector instructions but if they won't work in this scenario due to the register size it should be fairly straightforward to implement the pcodeops in java. I haven't looked in a while though.

[chaoticgd]

Testing it again it seems to work fine. I think I just forgot to re-disassemble some of the code I was analysing the first time. I'd say it's ready to merge.

[astrelsky]

If either of you would like, I can introduce a context register for vu micro instructions. It would just check the memory block the instructions are in and set accordingly.

[chaoticgd]

@astrelsky

I like your idea of using a subtable. It certainly seems cleaner than the alternative. My version of cop2.sinc already has an newline at the end of the file. Can you clarify? Implementing a context register seems like a good idea. You should open a new PR after this one is merged.

[astrelsky]

@astrelsky

I like your idea of using a subtable. It certainly seems cleaner than the alternative. My version of cop2.sinc already has an newline at the end of the file. Can you clarify? Implementing a context register seems like a good idea. You should open a new PR after this one is merged.

About the newline, I didn't realize it was in a deletion and not an addition. My mistake.

I'll see about doing the context register when I have some free time. I've been looking at the implementations of the vector instructions in the arm_neon sleigh files but I can't seem to wrap my head around how it's being done.

Edit: I looked into a context register and it appears there is no way to fetch the memory block from the instruction state modifier. It would need to be set in advance probably in a leader. It may be best to see if we can get away without it first. I was able to create a couple vu lower instructions so a modifier may not be necessary.

[astrelsky]

I just discovered by a bit of digging in the java source that we can make the vf registers vector registers by setting the following in the r5900.pspec file.

<register_data>
    <register name="vf_num" vector_lane_sizes="4"/>
</register_data>

[beardypig]

@astrelsky amazing!

[astrelsky]

I'm going to try setting up some vector lanes for the general purpose registers. If it works the way I think it will then it will simplify many or the mmi parallel instructions.

I think vadd now becomes vf0 f+ vf1 but I'm not 100% sure because I ran out of time to test before class.

Edit: It does not appear to be that straightforward.

[chaoticgd]

@astrelsky Good catch.

[beardypig]

Thanks @chaoticgd and @astrelsky, I'm going to get this merged along with #24.