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beardypig / ghidra-emotionengine

Ghidra Processor for the Play Station 2's Emotion Engine MIPS based CPU
Apache License 2.0
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Fix some vector commands for shared input/output registers. #44

Closed PFedak closed 3 years ago

PFedak commented 3 years ago

These commands are commonly called with the same register as rd and either rt or rs. Written naively, bits to be read will be clobbered by writes. The assignments can simply be reordered in cases where the collapsed command has no cycle.

Also add a missing swap in pexch.

PFedak commented 3 years ago

This actually came up in the same function that led me to notice the issues in the previous PR, truly a goldmine. I'm not sure this is exhaustive, I just did a search for a regex pattern of a write to RD128 followed by a read from the same bit range in RS or RT. pcpyh fits this pattern, too, but is correct as written.

I had wanted to just use a single 128-bit temp register for some of these to avoid hurting code readability, but sleigh complained. Is there some way around that I'm missing?

beardypig commented 3 years ago

Unfortunately Sleigh doesn't support 128 bit very well. (NationalSecurityAgency/ghidra#206)

astrelsky commented 3 years ago

Unfortunately Sleigh doesn't support 128 bit very well. (NationalSecurityAgency/ghidra#206)

It doesn't support a varnode larger than 64 bits at all.

PFedak commented 3 years ago

Were there any changes you wanted to see in this PR?

astrelsky commented 3 years ago

Were there any changes you wanted to see in this PR?

I haven't actually taken a look yet. Can do tomorrow.

astrelsky commented 3 years ago

If these are just reordered then it is ok with me.