FEATURE REQUEST: Please add support for CLR.Q instruction of Apollo 68080 CPU

[GunnarVB]

File: opcodes/m68k-opc.c

Please add this line to enable CLR.Q

{"clrb", 2,     one(0041000),   one(0177700), "$s", m68000up | mcfisa_a },
{"clrw", 2,     one(0041100),   one(0177700), "$s", m68000up | mcfisa_a },
{"clrl", 2,     one(0041200),   one(0177700), "$s", m68000up | mcfisa_a },
**{"clrq", 2,     one(0127000),   one(0177700), "$s", m68080 }, // APOLLO 68080** 

-- Question 2: For C code like this:

void clrstruct (int * ptr)
{
   ptr[10]=0;
   ptr[11]=0;
}

GCC will right now create this:

_clrstruct:
        clr.l (40,a0)
        clr.l (44,a0)
        rts

Could GCC be enhanced to use the CLR.Q opcode here for setting the two longs in one instruction?

Many thanks in advance!!

[bebbo]

please test

[GunnarVB]

Hallo Bebbo, Thank you for the swift action.

I tested the current GCC/binutils and I'm getting this error when compiling a program with it.

insn does not satisfy its constraints: } ^ (insn 1426 171 174 20 (set (reg/v:DI 237 [ __comp ]) (const_int 0 [0])) /home/avb/ApolloCrossDev/Compilers/GCC-6.50/ApolloCrossDev/lib/gcc/m68k-amigaos/6.5.0b/include/c++/bits/stl_algo.h:1965 60 {*movdi_const0_68080} (nil))

Does this tell you something?

[bebbo]

see https://github.com/bebbo/gcc/issues/218 registers are allowed too now

[GunnarVB]

Thank you very much! Bebbo you are great!

I close this now