FEATURE REQUEST: Please enable MVZ,MVS,MOVI,MOV3Q instruction for Apollo 68080 CPU

Dear Stefan,

could you please enable the MVZ,MVS,MOVI,MOV3Q instruction in GAS

Please insert the below marked rows to this file: projects/binutils/opcodes/m68k-opc.c

{"mvzw", 2,     one(0070700),   one(0170700), "*wDd", mcfisa_b | mcfisa_c },

**{"moviwl",4,    one(0121000),   one(0177700), "#w$s", m68080 }, // Apollo 68080 
{"mov3ql", 2,   one(0120100),   one(0170700), "xd%s", m68080 }, // Apollo 68080
{"mvsb", 2,     one(0120400),   one(0170700), "*bDd", m68080 }, // Apollo 68080
{"mvsw", 2,     one(0120500),   one(0170700), "*wDd", m68080 }, // Apollo 68080
{"mvzb", 2,     one(0120600),   one(0170700), "*bDd", m68080 }, // Apollo 68080
{"mvzw", 2,     one(0120700),   one(0170700), "*wDd", m68080 }, // Apollo 68080**

{"movesb", 4,   two(0007000, 0),     two(0177700, 07777), "~sR1", m68010up },

Many thanks in advance!!

In GCC to enable them, please change the following:

File: gcc/config/m68k/m68k.h line 277:

#define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC || TARGET_68080)

File: gcc/config/m68k/m68k.c line: 3516

/* Return true if I can be handled by ISA B's mov3q instruction.  */

bool
valid_mov3q_const (HOST_WIDE_INT i)
{
  return (TARGET_68080 || TARGET_ISAB) && (i == -1 || IN_RANGE (i, 1, 7));
}

line: 3525

/* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
   I is the value of OPERANDS[1].  */

static const char *
output_move_simode_const (rtx *operands)
{
  rtx dest;
  HOST_WIDE_INT src;

  dest = operands[0];
  src = INTVAL (operands[1]);
  if (src == 0 && (DATA_REG_P (dest) ))         // For clear DN MOVEQ is best
    return "moveq #0,%0";
  else if (src == 0 && MEM_P (dest)             // For memory use CLR
                                                // but not for IO register on 68000
          && ((TARGET_68010 || TARGET_COLDFIRE) || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
    return "clr%.l %0";
  else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
    return "mov3q%.l %1,%0";
  else if (src == 0 && ADDRESS_REG_P (dest))    // For AN always use SUBA
    return "suba%.l %0,%0";
  else if (DATA_REG_P (dest) && IN_RANGE (src, -0x80, 0x7f))
    return "moveq %1,%0";
  else if (DATA_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff) && TARGET_68080)
    return "moviw%.l %1,%0";
  else if (DATA_REG_P (dest))
    return output_move_const_into_data_reg (operands);
  else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
    {
      if (valid_mov3q_const (src))
        return "mov3q%.l %1,%0";
      return "move%.w %1,%0";
    }
  else if (MEM_P (dest)
           && GET_CODE (XEXP (dest, 0)) == PRE_DEC
           && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
           && IN_RANGE (src, -0x8000, 0x7fff))
    {
      if (valid_mov3q_const (src))
        return "mov3q%.l %1,%-";
      return "pea %a1";
    }
  else if (IN_RANGE (src, -0x8000, 0x7fff) && TARGET_68080){
    return "moviw%.l %1,%0";
  }else if (DATA_REG_P (dest) && IN_RANGE (src, 0, 0xFfff) && TARGET_68080){
    return "movzw%.l %1,%0";
  }
    return "move%.l %1,%0";
}

file m68k.md

line 3811

(define_insn "andsi3_5200"
  [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
        (and:SI (match_operand:SI 1 "general_operand" "%0,0")
                (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
  "TARGET_COLDFIRE OR TARGET_68080"
{
  if (ISA_HAS_MVS_MVZ
      && DATA_REG_P (operands[0])
      && GET_CODE (operands[2]) == CONST_INT)
    {
      if (INTVAL (operands[2]) == 0x000000ff)
        return "mvz%.b %0,%0";
      else if (INTVAL (operands[2]) == 0x0000ffff)
        return "mvz%.w %0,%0";
    }
  return output_andsi3 (operands);
})

Many thanks!!!

bebbo / binutils-gdb

FEATURE REQUEST: Please enable MVZ,MVS,MOVI,MOV3Q instruction for Apollo 68080 CPU #39