This PR fixes the warning for SPIR-V Kernels generating vector-16 instructions (e.g., Float16).
Problem description
The issue is that the spirv-val was emitting an error due to a missing SPIR-V capability in the generated SPIR-V kernels.
This PR adds the capability when it is required.
Backend/s tested
This PR only affects the SPIR-V backend,
[ ] OpenCL
[ ] PTX
[X] SPIRV
OS tested
Mark the OS where this PR is tested.
[X] Linux
[ ] OSx
[ ] Windows
Did you check on FPGAs?
If it is applicable, check your changes on FPGAs.
[ ] Yes
[X] No
How to test the new patch?
$ make BACKEND=spirv
$ tornado-test --printKernel --debug -V uk.ac.manchester.tornado.unittests.vectortypes.TestFloats#testSimpleDotProductFloat16
....
[SPIRV-Runtime] SPIRV Registering VM Intrinsics Plugins - pending
SPIRV-File : /tmp/tornadoVM-spirv/11047078642496-s0.t0dotMethodFloat16.spv <<< Kernel File
[SPIRV-Runtime] Set SPIR-V entry point: dotMethodFloat16
$ spirv-val /tmp/tornadoVM-spirv/11047078642496-s0.t0dotMethodFloat16.spv <<< Note that the kernel file is different per execution
If nothing is emitted in the last instruction, then the kernel is correct.
Description
This PR fixes the warning for SPIR-V Kernels generating vector-16 instructions (e.g., Float16).
Problem description
The issue is that the
spirv-valwas emitting an error due to a missing SPIR-V capability in the generated SPIR-V kernels. This PR adds the capability when it is required.Backend/s tested
This PR only affects the SPIR-V backend,
OS tested
Mark the OS where this PR is tested.
Did you check on FPGAs?
If it is applicable, check your changes on FPGAs.
How to test the new patch?
If nothing is emitted in the last instruction, then the kernel is correct.