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beifen / neurorighter

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Problems with ADC/DAC polling period selection #27

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
What steps will reproduce the problem?
1. Changing the ADC polling period to a lower value than default

- This is several issues compounded into one

1. Input and output should be locked at the same loop speed. There is no 
advantage for a closed loop system to have two polling periods since one 
process will always be waiting for the slower one.
2. When you decrease the input polling period, then increase it, the NR's 
persistent data buffers are not resized leading to an out of range exception.
3. The aux plotting gets all screwed up for shorter polling periods

Original issue reported on code.google.com by jonathan...@gmail.com on 2 Nov 2011 at 3:49

GoogleCodeExporter commented 9 years ago 
1. There is an advantage to having two speeds, for instance if you are using a 
non-native output device like the arduino
2. This is fixed.
3. This is fixed.

Original comment by jonathan...@gmail.com on 3 Apr 2012 at 3:46