Cannot run examples: 'clk' signal not found

[aubindetrez]

I tried to run the examples but I get the following error (For all of them):

0.000ns Couldn't get handle from name $unit.clk                                                     
thread '<unnamed>' panicked at 'Could not get object with name $unit.clk', src/signal.rs:150:33

I am using Icarus Verilog version 11.0.

After debugging the VPI module for a while I was able to fix it by removing $unit in the vvp file

#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi";
S_0x55d49b261d90 .scope package, "$unit" "$unit" 2 1; # Delete this one
 .timescale 0 0;  # And delete that one
S_0x55d49b261f20 .scope module, "dut" "dut" 3 3;
 .timescale -12 -12;
    .port_info 0 /INPUT 1 "rstn";
    .port_info 1 /INPUT 1 "clk";
[...]

Looks like the problem comes from get_full_name() in src/vpi.rs (calling vpi_get_str). https://github.com/benbr8/rstb/blob/169ab0c4cc9125f5c389e325cf58d178b2d892c2/src/vpi.rs#L203-L205 That function is returning $unit instead of dut (for my good run).

I start to wonder if the problem is not in get_root_handle() (the obj argument given to get_full_name() come from that function) https://github.com/benbr8/rstb/blob/169ab0c4cc9125f5c389e325cf58d178b2d892c2/src/vpi.rs#L216-L218

[aubindetrez]

Looks like I found the problem.

Here are the examples:

• [x] test_axis_fifo - PASS
• [x] test_dff - PASS
• [x] test_verilog_types - PASS
• [x] test_concurrent_assertions - PASS

[benbr8]

Thanks for bringing this up and putting in the debug effort :)