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benjamin051000 / riscv-business

A RISC-V RV32I Core
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generate an exception when jumping to a non-aligned (4-bit alignment) instruction #3

Open benjamin051000 opened 1 month ago

benjamin051000 commented 1 month ago

From unpriv page 23:

An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not IALIGN-bit aligned. This exception is reported on the branch or jump instruction, not on the target instruction. No instruction-address-misaligned exception is generated for a conditional branch that is not taken.

IALIGN=32 in the base ISA.

benjamin051000 commented 1 month ago

Instruction-address-misaligned exceptions are reported on the branch or jump that would cause instruction misalignment to help debugging, and to simplify hardware design for systems with IALIGN=32, where these are the only places where misalignment can occur.