A four character buffer would be sufficient to catch most communication. It would require another timer ISR to periodically flush the UART FIFO. This would lead to lower interrupt saturation but higher complexity. Also, a message may have to wait the full timer period in order to be received.
A four character buffer would be sufficient to catch most communication. It would require another timer ISR to periodically flush the UART FIFO. This would lead to lower interrupt saturation but higher complexity. Also, a message may have to wait the full timer period in order to be received.