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benreynwar / fusesoc_generators

Add generators to fusesoc so that depenedencies can be generated from generic parameters.
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Use parser instead of calling GHDL #2

Open olofk opened 7 years ago

olofk commented 7 years ago

Without having checked this myself, I believe there is Python code in either HDLMake or VUnit for parsing Verilog/VHDL modules/entities. No idea how hard they will be to extract though.

benreynwar commented 7 years ago

Yeah, I'd definitely like to replace the calling of GHDL by a parser too, but it's a really big task!

Extracting the hierarchy wouldn't be too hard. The difficult bit would be resolving the generic parameters. In VHDL the generic parameters can be produced by arbitrary functions so we'd basically need full-blown elaboration in python. I know the VUnit parser isn't up to this task because I'm using it for another project, but @paebbels has one that I'm meaning to look into sometime.

olofk commented 7 years ago

Cool. Sounds like you've done your homework :)

VHDL is notoriously hard to parse