Error thrown by %read while reading Verilog RTL

[aman-goel]

I was trying to use ABC command %read to read a Verilog RTL file. The command throws a " stack smashing detected error" at the assign statements (example: while reading line 11 assign w_01_ = X + 4'h1; for the example below).

module counter(clk, prop_neg, en);
  wire [3:0] w_00_;
  wire [3:0] w_01_;
  wire w_02_;
  wire [3:0] w_03_;
  reg [3:0] X;
  input clk;
  input en;
  wire prop;
  output prop_neg;
  assign w_01_ = X + 4'h1;
  assign w_02_ = X == 4'hf;
  assign prop_neg = ! prop;
  assign prop = X != 4'h0;
  initial
    X = 4'h1;
  always @(posedge clk)
      X <= w_00_;
  assign w_03_ = w_02_ ? 4'h1 : w_01_;
  assign w_00_ = en ? w_03_ : X;
endmodule

Is there any specific restriction on Verilog designs ABC can read as of now?

[zhanghongce]

I have a suggestion of using Yosys as the frontend parser and then generate some format (Aig/Blif) that ABC takes...