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berkeley-abc / abc

ABC: System for Sequential Logic Synthesis and Formal Verification
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abc fails to read bluespec generated verilog #181

Open iamkarthikbk opened 1 year ago

iamkarthikbk commented 1 year ago

Hi. I've been trying to get abc to read my generated verilog files. I generate these using the bluespec compiler. However, when I try to read or read_verilog this generated file, I see the following error:

> abc
UC Berkeley, ABC 1.01 (compiled Sep 21 2022 13:57:05)
abc 01> read_verilog mk_sample_design.v
mk_sample_design.v (line 24): Cannot read "module" directive.
Reading network from file has failed.
abc 01> read mk_sample_design.v
mk_sample_design.v (line 24): Cannot read "module" directive.
Reading network from file has failed.

Yosys on the other hand, does not fail to read this file. Could someone help me understand what I need to do in order to get abc to read this generated file? thanks in advance :)

alanminko commented 1 year ago

ABC's Verilog parser is notoriously dysfunctional. It is better to read the files into Yosys and output AIG or BLIF, which can be read into ABC.

On 9/22/2022 11:17 PM, Karthik B K wrote:

Hi. I've been trying to get abc to read my generated verilog files https://github.com/iamKarthikBK/sample_design/blob/main/build/hw/verilog/mk_sample_design.v. I generate these using the bluespec compiler https://github.com/B-Lang-org/bsc. However, when I try to |read| or |red_verilog| this generated file, I see the following error:

|> abc UC Berkeley, ABC 1.01 (compiled Sep 21 2022 13:57:05) abc 01> read_verilog mk_sample_design.v mk_sample_design.v (line 24): Cannot read "module" directive. Reading network from file has failed. abc 01> read mk_sample_design.v mk_sample_design.v (line 24): Cannot read "module" directive. Reading network from file has failed. |

Yosys on the other hand, does not fail to read this file. Could someone help me understand what I need to do in order to get |abc| to read this generated file? thanks in advance :)

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