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berkeley-abc / abc

ABC: System for Sequential Logic Synthesis and Formal Verification
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Abc_AigUpdateLevelR_int: Assertion `Abc_ObjIsNode(pNode)' failed for some commands #271

Closed YiKangOY closed 8 months ago

YiKangOY commented 9 months ago

Hi, I have an int2float circuit, I transformed it in to aiger by yosys, then I want to synthesize it through abc.

When I try "rf" or "resub", it will trigger Abc_AigUpdateLevelR_int: Assertion `Abc_ObjIsNode(pNode)' failed

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The aig and verilog file processed by Yosys is attatched. abc_int2float.zip

Any help or suggestions will be appreciated! Thanks!

Outsider225 commented 9 months ago

I met the same problem.

I transform vtr and koios benchmarks into blif using Odin II, then run abc with command "read stereovision0.odin.blif; strash; resyn2; if -K 6; print_stats; write_hie stereovision0.odin.blif stereovision0.abc_no_clk.blif; time" Some of the benchmarks will trigger abc: src/base/abc/abcAig.c:1134: Abc_AigUpdateLevelR_int: Assertion `Abc_ObjIsNode(pNode)' failed., for example, stereovision0, tiny_darknet_like.medium.

I am using abc commit 16a3c5f. After checkout to a much older version b2aa245, the problem is gone.

YiKangOY commented 9 months ago

Thanks, I will give it a try.

wjrforcyber commented 9 months ago

I believe this issue is discussed by a lot of folks from Yosys and OpenLane, checkout this thread. Replacing all rewrite/refactor with drw/drf (-l) may solve the problem.

YiKangOY commented 8 months ago

I guess we can follow @wjrforcyber 's suggest, try to use drw and drf. Thanks! Closing this issue.