Is a deep search for repositories planned?

[Paebbels]

Hello,

I tested the vhdl uart example search string. It lists all repositories containing uart in the name.

We are providing a big IP core library called PoC Library, which also includes an UART component written in VHDL. PoC is listed as under vhdl on pages 2 (stars), 2 (last update) or 3 (forks), which is good. But I would be good, if we could be found for in combination with a IP core name like uart.

Is there a way that such repositories get found easier?

[berndca]

Thats a good point! I believe there may be a few IP repos with a similar situation. The current data is extracted from the Github api. Other that knowing the files in the repo Github has no way of figuring out that there is a UART in src/io. This makes it very difficult to detect in an automated search. I would suggest to put this info together manually (IP block name and description) and feed it into the data compilation. Would this work for you? Could you please provide this data? How should I display IP blocks within a repo?

Thanks, Bernd

[Paebbels]

Hello Bernd,

Could you please provide this data?

all our IP cores are listed in config.entity.ini. We use a special naming scheme to create a virtual hierarchy (VHDL doesn't support that yet). The hierarchy itself is stored in config.structure.ini. A Python package exists to handle these INI files. We could add a short name to each IP core description node if this helps.

A human readable documentation and full hierarchical IP core list is available at poc-library.rtfd.org.

---

How should I display IP blocks within a repo?

Hmmm, good question! Just thinking loud:

• Add a column to denote N (sub) IP cores per repository.
• Create a separate list for libraries.
• Add an extend button
• ...

Kind regards Patrick

[berndca]

Patrick,

thanks. I'll have a look at the meta data files you pointed out. I'll go ahead and extract the IP info. When I quickly browsed through the repo it seemed like perhaps 80-90% of the blocks should be listed. There are some "helper" modules which we might skip. I should have an initial list tomorrow evening your time.

Thanks, Bernd

[Paebbels]

Yes, not all IP cores are useful in a standalone setup. But they got an entry to model dependencies. Are you interested in VHDL designs or the language itself?

If you have question, please contact me e.g. at Gitter.

[berndca]

Here is what I found so far in the PoC repo. Please review and comment. I intentionally skipped anything wrapper and Altera/Xilinx. Did I miss anything? Would you like me to add or change descriptions? Also could you please let me know the status of these blocks? Which blocks have been validated in an FPGA? Have any blocks seen silicon?

Thanks, Bernd

Name	Description
arith_addw
arith_addw
arith_carrychain_inc
arith_convert_bin2bcd
arith_counter_bcd	BCD (Binary-Coded Decimal) counter.
arith_counter_free
arith_counter_gray	Gray-Code counter.
arith_counter_ring	Johnson counter
arith_firstone
arith_muls_wide
arith_prefix_and
arith_prefix_or
arith_prng	Pseudo Random Number Generator (PRNG).
arith_same
arith_scaler
arith_shifter_barrel
arith_sqrt
bus_Arbiter	a generic arbiter implementation with selectable port count
bus_stream	PoC.stream bus
cache_par	Cache with parallel tag-unit and data memory
cache_replacement_policy	Wrap different cache replacement policies
cache_tagunit_par	Tag-unit with fully-parallel compare of tag
cache_tagunit_seq	Tag-unit with sequential compare of tag
comm_crc	generic Cyclic Redundancy Check (CRC)
comm_scramble	generic LFSR based scrambler
ddrio_in	Dual-Data-Rate Input
ddrio_inout	Dual-Data-Rate Input and Output
ddrio_out	Dual-Data-Rate Output
dstruct_deque	deque (double-ended queue)
dstruct_stack	stack (LIFO)
fifo_cc_got	regular FIFO (one common clock, got-interface)
fifo_cc_got_tempgot	regular FIFO (one common clock, got-interface), extended by a transactional tempgot-interface (read-side)
fifo_cc_got_tempput	regular FIFO (one common clock, got-interface), extended by a transactional tempput-interface (write-side)
fifo_dc_got	cross-clock FIFO (two related clocks, got-interface)
fifo_ic_assembly	address-based FIFO stream assembly (two independent clocks)
fifo_ic_got	cross-clock FIFO (two independent clocks, got-interface)
mem_is61lv	ISSI - IS61LV SRAM controller
mem_is61nlp	ISSI - IS61NLP SRAM controller
mem_lut	Lookup-Table (LUT) implementations
mem_ocram	On-Chip RAM abstraction layer
mem_ocrom	On-Chip ROM abstraction layer
mem_sdram	SDRAM controllers
misc_filter	contains 1-bit filter algorithms (and, or, mean)
misc_FrequencyMeasurement	measures a input frequency relativ to a reference frequency
misc_gearbox	gearbox bus interface converter
misc_sync	offers clock-domain-crossing (CDC) modules
net_arp_BC_Receiver	Address Resolution Protocol - ARP BroadCast Receiver
net_arp_BC_Requester	Address Resolution Protocol - ARP BroadCast Requester
net_arp_Cache	Address Resolution Protocol - ARP Cache
net_arp_IPPool	Address Resolution Protocol - ARP IPPool
net_arp_UC_Receiver	Address Resolution Protocol - ARP UniCast Receiver
net_arp_UC_Responder	Address Resolution Protocol - ARP UniCast Responder
net_ipv4_FrameLoopback	Internet Protocol - Version 4 Loopback
net_ipv4_RX	Internet Protocol - Version 4 RX
net_ipv4_TX	Internet Protocol - Version 4 TX
net_ipv6_FrameLoopback	Internet Protocol - Version 6 Loopback
net_ipv6_RX	Internet Protocol - Version 6 RX
net_ipv6_TX	Internet Protocol - Version 6 TX
net_mac_FrameLoopback
net_mac_RX_DestMAC_Switch
net_mac_RX_SrcMAC_Filter
net_mac_RX_Type_Switch
net_mac_TX_DestMAC_Prepender
net_mac_TX_SrcMAC_Prepender
net_mac_Type_Prepender
net_udp_FrameLoopback
net_udp_RX
net_udp_TX
pmod_KYPD	a 16-button (4x4) keypad
pmod_SSD	a 2 digit 7-segment display (SSD)
pmod_USBUART	a USB to UART bridge (FTDI FT232RQ)
sort_lru_cache	Optimized LRU list implementation for Caches.
sort_lru_list	List storing key-value pairs in recently-used order
sortnet_BitonicSort	bitonic sorter as a sorting network
sortnet_OddEvenMergeSort	odd-even sorter as a sorting network
sortnet_OddEvenSort	odd-even sorter as a sorting network
stat_Average
stat_Histogram
stat_Maximum
stat_Minimum
uart	Simple UART

[Paebbels]

Hello Bernd,

here are my remarks:

• arith_addw is duplicated (one is from a Xilinx directory, thus it's a special Xilinx optimized variant)
• addw = width operand addition (e.g. 256 to 4096 bits)
• carrychain_inc is a Xilinx specific carray chain abstraction and a helper -> can be removed
• counter_free - free running counter
• convert_bin2bcd - convert binary numbers to binary coded decimals (BCD)
• firstone - find the index if the first one in a vector
• prefix_and/_or are charry chain improved and and or operations (faster then normal LUT based gates if many inputs are used)
• scaler - fixed point scaling unit (y := (x * A) / B)
• shifter_barrel - is a barrel shifter with multiple modes
• sqrt - square root
• where is arith_div - our fixed point division?
• you group some namespace, which I would consider as independent units
  • bus_stream
  • ocram / ocrom
  • filter
  • gearbox
  • sync
• on the otherhand, you can group all network layer modules depending on the protocol I don't think users might use a udp_RX without a udp_TX, so I would list the wrapper module, because it represents one protocol layer ;)
• average = calculate the running average value if an input stream
• histogram = calculate a histrogram (distribution) of an input stream
• maximum = calculate the maximums of an input stream
• minimum = calculate the minimums of an input stream

Regarding the quality of each module:

• actually, every module should have been used in a productive FPGA design (we mostly collect used subcomponents)
• mostly all modules have testbenches (see the tb folder, with the same structure as src)
• we have a Travis-CI integration, so we check our testbenches after reach push on Travis and generate a testbench report: https://travis-ci.org/VLSI-EDA/PoC/jobs/159675873#L497

The last run is broken due to a discovered bug in GHDL - will be fixed soon. Does this help you further?

Kind regards Patrick

[berndca]

Patrick,

thanks for the feedback! I extracted the info from the local README.md files since this was the only place I could easily find descriptions. I was led astray by the link target of arith_div which points to arith_addw. Probably a typo?

I incorporated your descriptions and assigned the status FPGA verified to all components. At this point the plan is to list all ip blocks without any extra grouping, i.e. if you search for PoC you will get 80 rows with VLSI-EDA/PoC: - . I consider the user interface work in progress and there is a good chance that things might change in the future. However at this point I'd like to get some more feedback first.

BTW, I ran into some trouble trying to set up the repo on my Linux (Ubuntu 16) machine. The poc.sh crashed the terminal and I could not access (Permission denied.) the links to the documentation in the top level README. You probably need to logout of github to duplicate this problem.

Thanks, Bernd