bespoke-silicon-group bsg_fakeram issues - Githubissues

bespoke-silicon-group / bsg_fakeram

fakeram generator for use by researchers who do not have access to commercial ram generators

BSD 3-Clause "New" or "Revised" License

32 stars 14 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

Adding latch_last_read process flag for simulation models

#16 stdavids closed 1 year ago
0
Add Verilog time check signal expansion option

#15 derekcom17 closed 2 years ago
1
Add option to configure pin length

#14 derekcom17 closed 2 years ago
0
unable to generate fakeram for sky130

#13 vijayank88 opened 2 years ago
9
Added Sky130 example config file and comparison with OpenRAM SRAMs

#12 lakshmi-sathi closed 3 years ago
3
Add SKY130 example configurations?

#11 mithro opened 3 years ago
8
ASAP7 support?

#10 mithro opened 3 years ago
2
removed <90nm limit check on technology node used

#9 lakshmi-sathi closed 3 years ago
13
default_max_transition is 0.0

#8 rovinski closed 4 years ago
1
Updates to cacti config and cacti patch to address issues with OS/GCC differences.

#7 stdavids closed 4 years ago
2
Allow bsg_fakeram to be installed in a shared directory

#6 rbarzic closed 4 years ago
1
ValueError: cannot convert float NaN to integer

#5 AEstein closed 4 years ago
0
Grid alignment issues using bsg_fakeram

#4 tajayi closed 4 years ago
4
Invalid VDD/VSS port shapes in LEF

#3 tajayi closed 5 years ago
5
Example sram_32x32_1rw configuration fails to generate

#2 tajayi opened 5 years ago
9
Update run.py shebang to be more portable

#1 tajayi closed 5 years ago
1