A CSR instruction in ID that accesses fflags should stall (stall_fcsr) until all the float instructions that could update fflags (e.g. fpu_float, fpu_int, fdiv ops) and have already been issued, finish accruing the exception flag. Currently, the exception in fcsr module is being triggered even when the CSR instruction modifies only frm (rounding mode). So the assertion is being fixed to prevent this false alarm.
A CSR instruction in ID that accesses fflags should stall (stall_fcsr) until all the float instructions that could update fflags (e.g. fpu_float, fpu_int, fdiv ops) and have already been issued, finish accruing the exception flag. Currently, the exception in fcsr module is being triggered even when the CSR instruction modifies only frm (rounding mode). So the assertion is being fixed to prevent this false alarm.