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bespoke-silicon-group / bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality
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Tracking: Parameter-Controlled Bind Statements in Verilator #639

Open drichmond opened 2 years ago

drichmond commented 2 years ago

Filing this for tracking, and so we can link it to the Verilator issue we will file.

In #636, we added several lines that clock gate the parameter-controlled bind statements in Verilator. This is because Verilator seems to instantiate this modules, even when the parameters supposedly prevent their instantiation.

They look roughly like this:

,.clk_i(clk_i && $root.`HOST_MODULE_PATH.testbench.enable_vcore_profiling_p)

Similar statements exist for enable_cache_profiling_p enable_router_profiling_p enable_vcore_pc_coverage_p and enable_vanilla_core_trace_p.

When this bug is fixed in Verilator, we need to undo this change and revert back to the original source.

dpetrisko commented 2 years ago

Found the issue, it got ported over from their old issue tracker: https://github.com/verilator/verilator/issues/1501