Closed tommydcjung closed 1 year ago
Code looks good. Does it make sense to have ruche_factor = 0 decompose into a regular mesh? Could remove some of these mostly identical hierarchies
Code looks good. Does it make sense to have ruche_factor = 0 decompose into a regular mesh? Could remove some of these mostly identical hierarchies
Ideally, we would do that. Although there is duplication of code, there is less uncertainty for the physical design tools. We have to remove the ruche ports as we place and route the lower level modules, so the ETM block will not have contain any info on the removed ports. But then when we are synthesizing the higher level module using the ETM, the verilog code will expect there to be some ports.
Ah, that makes sense. zero-width signals strike again
Adding BSG_MACHINE_NETWORK_CFG again to support 2D mesh.