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bespoke-silicon-group / bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality
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Update regfile_synth for ultrascale plus fpga mapping #659

Closed gaozihou closed 2 years ago

gaozihou commented 2 years ago

This PR resolves the regfile mapping problem on the Ultrascale Plus FPGA. currently regfile is mapped as registers instead of LUTRAMs. The mapping problem can be resolved by unpacking the arrays and tweaking the combinational logics.

  1. It is functionally identical to the original version (verified with randomly-generated testbench in both VCS and Vivado simulators)
  2. ASIC resource utilization change is minimal (-0.1% area) after synthesis in DC
  3. LUT utilization on FPGA reduce by 15% in Vivado
gaozihou commented 2 years ago

Thanks Tommy!