This PR resolves the regfile mapping problem on the Ultrascale Plus FPGA. currently regfile is mapped as registers instead of LUTRAMs. The mapping problem can be resolved by unpacking the arrays and tweaking the combinational logics.
It is functionally identical to the original version (verified with randomly-generated testbench in both VCS and Vivado simulators)
ASIC resource utilization change is minimal (-0.1% area) after synthesis in DC
This PR resolves the regfile mapping problem on the Ultrascale Plus FPGA. currently regfile is mapped as registers instead of LUTRAMs. The mapping problem can be resolved by unpacking the arrays and tweaking the combinational logics.