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bespoke-silicon-group / bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality
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Fixes naming conventions for ready signals in bsg_manycore_link_to_ca… #671

Closed BrendenPage closed 1 year ago

BrendenPage commented 1 year ago

The ready_i signals in the bsg_manycore_link_to_cache modules are used as would be implied by a rv->& interface, assuming that bsg_cache's output signal represents a ready signal, which is currently under review as per this issue post: https://github.com/bespoke-silicon-group/basejump_stl/issues/605

In the meantime, I propose that these signals are being properly used with a ready_and interface and should therefore be named as such for clarity.

BrendenPage commented 1 year ago

I'm going to re-submit this PR by first making a branch so I can continue work/push other commits regarding similar changes in other locations.