The ready_i signals in the bsg_manycore_link_to_cache modules are used as would be implied by a rv->& interface, assuming that bsg_cache's output signal represents a ready signal, which is currently under review as per this issue post: https://github.com/bespoke-silicon-group/basejump_stl/issues/605
In the meantime, I propose that these signals are being properly used with a ready_and interface and should therefore be named as such for clarity.
The ready_i signals in the bsg_manycore_link_to_cache modules are used as would be implied by a rv->& interface, assuming that bsg_cache's output signal represents a ready signal, which is currently under review as per this issue post: https://github.com/bespoke-silicon-group/basejump_stl/issues/605
In the meantime, I propose that these signals are being properly used with a ready_and interface and should therefore be named as such for clarity.