Closed BrendenPage closed 1 year ago
I do not have maintainer access to this repo, but this PR should be assigned to @tommydcjung and I would appreciate it if you had the chance to take a look. :)
@BrendenPage could you rebase this PR? Also, can you undo changes except for bsg_manycore_tile_vcache.v
and bsg_manycore_link_to_cache.v
? We don't use the other files currently and have no means to test.
@tommydcjung I've rebased the changes onto master
and reverted the changes to unused files.
The ready_i signals in the bsg_manycore_link_to_cache modules are used as would be implied by a rv->& interface, assuming that bsg_cache's output signal represents a ready signal, which is currently under review as per this issue post: https://github.com/bespoke-silicon-group/basejump_stl/issues/605
In the meantime, I propose that these signals are being properly used with a ready_and interface and should therefore be named as such for clarity.