Closed dpetrisko closed 1 year ago
Hm … what are the error messages? What are the types of each of the inputs to the ternary?
On Wed, Jan 25, 2023 at 11:46 PM Dan Petrisko @.***> wrote:
Minor change, VCS accepts it but Verilator and Xcelium do not.
By IEEE, I think the expression gets demoted to logic by the intermediate values, but I haven't delved in the specs about it
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https://github.com/bespoke-silicon-group/bsg_manycore/pull/690 Commit Summary
- ecce28c https://github.com/bespoke-silicon-group/bsg_manycore/pull/690/commits/ecce28c27ab3ed19a2870643bed960d6004a8ecd Update vanilla_core.v
- c9da43f https://github.com/bespoke-silicon-group/bsg_manycore/pull/690/commits/c9da43f0a6904a846a44790d2cfb8674e6aa30d6 Update vanilla_core.v
File Changes
(1 file https://github.com/bespoke-silicon-group/bsg_manycore/pull/690/files)
- M v/vanilla_bean/vanilla_core.v https://github.com/bespoke-silicon-group/bsg_manycore/pull/690/files#diff-fb58cb18cecd8bd90b1f0c414b758596888c19efed071a93ad31af272f6d1552 (4)
Patch Links:
- https://github.com/bespoke-silicon-group/bsg_manycore/pull/690.patch
- https://github.com/bespoke-silicon-group/bsg_manycore/pull/690.diff
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%Error-ENUMVALUE: <PATH>/zynq-parrot/cosim/import/bsg_manycore/v/vanilla_bean/vanilla_core.v:1638:17: Illegal implicit conversion to enum 'bsg_vanilla_pkg::frm_e' from 'logic[2:0]' (IEEE 1800-2017 6.19.3)
: ... In instance top.top_fpga_inst.DUT.py[0].podrow.px[0].pod.mc_y[0].mc_x[0].mc.y[0].x[0].tile.proc.h.z.vcore
: ... Suggest use enum's mnemonic, or static cast
1638 | assign fpu_rm = (id_r.instruction.funct3 == eDYN)
frm_e fpu_rm;
assign fpu_rm = frm_e'((id_r.instruction.funct3 == eDYN) // logic [2:0]
? frm_r // frm_e
: id_r.instruction.funct3); // logic [2:0]
FWIW, I have had to make similar changes to BP to fix XSIM compatibility over the years, where old versions would segfault with no error (very fun). enum implicit casting seems to be an edge case for lots of tools
Minor change, VCS accepts it but Verilator and Xcelium do not.
By IEEE, I think the expression gets demoted to logic by the intermediate values, but I haven't delved in the specs about it