Extremely long lines in generated verilog can cause yosys to crash

[tajayi]

Extremely long lines in generated verilog can cause yosys to crash.

1. Executing Verilog-2005 frontend: ./designs/src/ariane/ariane.sv2v.v
Parsing Verilog input from `./designs/src/ariane/ariane.sv2v.v' to AST representation.
input buffer overflow, can't enlarge buffer because scanner uses REJECT

See attached files from sv2v. Simply breaking up the super long lines resolved ths. Co-allating the original verilog files can be a bit challenging so hoping the elab.v works as a starting point ariane.tar.gz

[tajayi]

This no longer seems to be an issue in the latest (using no_always_at_redux_opt as well)