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bespoke-silicon-group / bsg_sv2v

A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
BSD 3-Clause "New" or "Revised" License
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always@ reduction fails in swerv design #12

Closed tajayi closed 4 years ago

tajayi commented 4 years ago

The always@ reduction fails in swerv design with the following error

INFO: Performing wire/reg declartion optimizations.
INFO: Performing always@ reduction optimizations.
Traceback (most recent call last):
  File "/net/trenton/x/ajayi/projects/OpenROAD/alpha-release/bsg_sv2v/scripts/py/bsg_elab_to_rtl.py", line 103, in <module>
    ast_always_at_redux_opt_inplace( ast )
  File "/net/trenton/x/ajayi/projects/OpenROAD/alpha-release/bsg_sv2v/scripts/py/bsg_ast_always_at_redux_opt_inplace.py", line 82, in ast_always_at_redux_opt_inplace
    ast_always_at_redux_opt_inplace(c)
  File "/net/trenton/x/ajayi/projects/OpenROAD/alpha-release/bsg_sv2v/scripts/py/bsg_ast_always_at_redux_opt_inplace.py", line 82, in ast_always_at_redux_opt_inplace
    ast_always_at_redux_opt_inplace(c)
  File "/net/trenton/x/ajayi/projects/OpenROAD/alpha-release/bsg_sv2v/scripts/py/bsg_ast_always_at_redux_opt_inplace.py", line 53, in ast_always_at_redux_opt_inplace
    if a.sens_list == always_blocks[bot_index].sens_list:
  File "/afs/eecs.umich.edu/cadre/software/anaconda3-2018.12/lib/python3.7/site-packages/pyverilog-1.1.3-py3.7.egg/pyverilog/vparser/ast.py", line 46, in __eq__
    if c != other_children[i]: return False
IndexError: tuple index out of range

Applying -no_always_at_redux_opt makes it generate.

swerv.tar.gz

tajayi commented 4 years ago

Closing this issue because no_always_at_redux_opt works