Yosys errors out due to non-synthesizable event list!

[tajayi]

On certain designs, yosys errors out with the following

Note: Assuming pure combinatorial block at ./designs/src/swerv/swerv_wrapper.sv2v.v:75 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
./designs/src/swerv/swerv_wrapper.sv2v.v:75: ERROR: Found non-synthesizable event list!

This seems to be related to the sensitivity list of the always@ block

  always @(posedge clk or N0) begin
    if(N0) begin
      dout[0] <= 1'b0;
    end else if(1'b1) begin
      dout[0] <= din[0];
    end 
  end

I am not sure if this is an issue with the original verilog file, however synthesis works in DC. I have observed this issue on another design that passed with always_at_redux_opt performed.

swerv.tar.gz

[tajayi]

validated in b379c0126d0eebeb1f2f87c0893777cdbab82d52