Missing module top

[tanglingshu]

After some digging, I think I found the issue why module top is not appearing. Take "bsg_cache.v" for example
1) The main design module, bsg_cache, is missing in the elab.v file 2) Tracing it back, it turns out that the renaming portion in the DC Synthesis run is not renaming the design module back to 'bsg_cache', thus in the elab.v file, there is no module named bsg_cache 3) This means that the top module wrapper will never occur because there is no bsg_cache to wrap

Temporary solution that worked for me so far: in bsg_sv2v/scripts/py/run_dc.tcl, I replaced the Rename portion of the code with the following code (taken from the bsg_target_design.dc.read_design.tcl from bsg_ppa_regression):

### Rename and set the real top-level design

# Check if the design name is found in the collection of designs. If not, then
# it either doesn't exist or it has been renamed (from parameters)
if { [sizeof_collection [get_designs -quiet ${DESIGN_NAME}]] == 0 } {

  set designs [get_designs -quiet -filter "@hdl_template == ${DESIGN_NAME}"]

  if { [sizeof_collection $designs] > 1 } {
    puts "BSG-Error: Toplevel design has multiple instances post-elaboration. This"
    puts "usually indicates that there are multiple parameterizations of the design."
    puts "This flow does not support different parameterizations of the top-level"
    puts "compile target, consider using a wrapper to uniqify the hierarchy for each"
    puts "parameter."
    exit -1
  }

  rename_design ${designs} ${DESIGN_NAME}
}

[stdavids]

Thanks Ling, do you have a means for me to run this for myself so I can fix the issue?

[tanglingshu]

Hi Scott, I've attached a bsg_launch_sync_sync.flist file. (make sure you remove the .txt extension since github wouldn't allow me to upload a .flist format).

Initial setup:

1) git clone basejump_stl somewhere and change the \<path-to-basejump> to the actual path of your basejump_stl in the 'bsg_launch_sync_sync.flist'. Alternatively, you can have a copy of bsg_launch_sync_sync.v somewhere and copy the path to that verilog file in your flist file.

2) In the Makefile, make sure you include the option 'SV2V_OPTIONS += -wrapper bsg_top'

To run, use the command (Assuming your flist file is in your sv2v directory):

make convert_sv2v DESIGN_NAME=bsg_launch_sync_sync DESIGN_FILELIST=bsg_launch_sync_sync.flist

you can then read the synth.log to see the Rename portion. You can also open up the elab.v file to see that there is no module named 'bsg_launch_sync_sync', which is required to generate the top wrapper.

bsg_launch_sync_sync.flist.txt

[stdavids]

Fixed in commit b734aed7fa30fc8bbf1ae50b2cf984654f81a66d.