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bespoke-silicon-group / bsg_sv2v

A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
BSD 3-Clause "New" or "Revised" License
30 stars 10 forks source link

Forcing DFFs with async reset or set to only trigger on the posedge in the sensitivity list. #16

Closed stdavids closed 4 years ago

taylor-bsg commented 4 years ago

Pretty sure we have negedge async reset flops in bsg_link?

On Mon, Apr 27, 2020 at 1:52 PM Scott Davidson notifications@github.com wrote:

Merged #16 https://github.com/bespoke-silicon-group/bsg_sv2v/pull/16 into master.

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stdavids commented 4 years ago

Correct, they get elaborated to the positive edge of an inverted clock signal.