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bespoke-silicon-group
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bsg_sv2v
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
BSD 3-Clause "New" or "Revised" License
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Adding support for async reset, enable flops
#17
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dpetrisko
closed
3 years ago
dpetrisko
commented
3 years ago
Adds support for async reset, enable flops (needed for HardFloat sqrt package)
Enhances sensitivity list comparison operator in pyverilog