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bespoke-silicon-group / bsg_sv2v

A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
BSD 3-Clause "New" or "Revised" License
30 stars 10 forks source link

Fixed output port name for REM_UNS_OP and REM_TC_OP synthetic operators #19

Closed stdavids closed 2 years ago

dpetrisko commented 2 years ago

Solves the problem!

dpetrisko commented 2 years ago

good to merge?