sv2v converter failed with AssertionError

[sakundu]

Hi,

I am trying to run sv2v and got the following error:

bsg_generic_modules.py", line 56, in SEQGEN
    assert not ( has_async_enable and has_sync_enable and has_async_data )
AssertionError

Here is the snippet of the elab.v verilog that results in such error:

\**SEQGEN**  id_available_q_reg_7_ ( 
      .clear(1'b0), 
      .preset(1'b0), 
      .next_state(id_available_d[7]), 
      .clocked_on(clk_i), 
      .data_in(1'b1), 
      .enable(rst_i), 
      .Q(id_available_q[7]), 
      .synch_clear(1'b0), 
      .synch_preset(1'b0), 
      .synch_toggle(1'b0), 
      .synch_enable(1'b1) );

Is there any easy way to fix it at our end by tweaking the input System Verilog or could you please address this error?

I have attached the elab.v file so that you can reproduce the above error.