DC systhesis error while using generated verilog file

bespoke-silicon-group / bsg_sv2v

A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.

BSD 3-Clause "New" or "Revised" License

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Open Jeremy-Jia opened 3 months ago

Jeremy-Jia commented 3 months ago

Error: ./dc32_top.sv2v.v:1122: The event depends on both edge and nonedge expressions, which synthesis does not support. (ELAB-91)

dpetrisko commented 1 month ago

Hi, can you post your input rtl?