error out earlier - Githubissues

bespoke-silicon-group / bsg_sv2v

A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.

BSD 3-Clause "New" or "Revised" License

30 stars 10 forks source link

Closed taylor-bsg closed 4 years ago

taylor-bsg commented 5 years ago

When there is a parsing error, e.g.,

Presto compilation terminated with 1 errors.

the tool does not stop immediately, but runs everything else, so you are forced to scroll back and try to hunt for the error in the output.

stdavids commented 5 years ago

Addressed in PR #5

stdavids commented 4 years ago

PR #5 merged into master