Closed hydra closed 2 weeks ago
Do you want to test this code? You can flash it directly from Betaflight Configurator:
#13604
(this pull request number) in the Select commit
field of the Configurator firmware flasher tab (you need to Enable expert mode
, Show release candidates
and Development
).WARNING: It may be unstable. Use only for testing!
@hydra : Strange thing is that IO_TAG(QUADSPI1_BK1_IO0_PIN) even compiles - the code was designed to generate error if such pin is used (pin not in port mask).
@hydra : Strange thing is that IO_TAG(QUADSPI1_BK1_IO0_PIN) even compiles - the code was designed to generate error if such pin is used (pin not in port mask).
The target I was testing on, the SPRacingH7EF (https://github.com/betaflight/config/pull/408) while having and using OctoSPI, does not enable the OctoSPI peripheral in BF itself. That code has been pending for a couple of years, though I'll probably get round to adding support for OctoSPI (on IO4-7) in memory mapped mode + config storage in memory mapped mode + SPI flash for logging, at some point.
here's some proof it works:
# version
# Betaflight / STM32H730 (SP7E) 4.5.0 Apr 29 2024 / 14:22:26 (8bce68bb03) MSP API: 1.46
# board: manufacturer_id: SPRO, board_name: SPRACINGH7EF
# status
MCU H730 Clock=520MHz, Vref=3.32V, Core temp=59degC
Stack size: 2048, Stack address: 0x2000f000
Configuration: CONFIGURED, size: 4223, max available: 65536
Devices detected: SPI:2, I2C:0
Gyros detected: gyro 1, gyro 2 locked dma
GYRO=ICM42688P, ACC=ICM42688P
OSD: SPRACINGOSD (30 x 16)
System Uptime: 524 seconds, Current Time: 2024-04-29T13:07:08.746+00:00
CPU:21%, cycle time: 125, GYRO rate: 8000, RX rate: 15, System rate: 9
Voltage: 1168 * 0.01V (3S battery - OK)
I2C Errors: 10
FLASH: JEDEC ID=0x00ef4015 2M
GPS: NOT ENABLED
Arming disable flags: RXLOSS ANGLE CLI MSP NO_ACC_CAL
Binaries for testing, for those that have the H7EF: betaflight_4.4.0_SPRACINGH7EF_b69371321c.zip
@hydra: It was quick grep, so the code is (probably) unused.
This should be revisited if more targets need exclusive pins. Maybe something like ` #define TARGET_IO_PORTB (0xffff & ~OCTOSPI_RESERVED_PORTB)
That make make sense at some point in the future. For now this PR's simple change will suffice and will let target authors have the same flexibility they previously had while providing sensible defaults in the base target.
This should be able to be overridden by targets. e.g. ones that use OctoSPI IO data lines 4-7 instead of 0-3.
Some history: Initial H730 targets always had their
TARGET_IO_*
defines in their target.h files, but these were moved to theSTM32H730
target at some point, but this causes compiler errors when the target redefines them.