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Betrusted main SoC design
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FPGA constraints: let Vivado derivate automatically more timing constraints? #10

Closed enjoy-digital closed 4 years ago

enjoy-digital commented 4 years ago

In the current design, all timing constraints are defined manually. Vivado (and open-source tools like NextPnr) are able to propagate constraints through clocking primitives and generate the output constraints automatically for most use-cases. Defining all constraints manually is of course valid but makes things difficult to change/maintain. Is it something wanted? Or would you be happy with a pull request that let the tool derivate automatically more timing constraints and only provide the useful ones?

bunnie commented 4 years ago

I had trouble getting the constraints to auto-propagate in Vivado, but maybe I was doing it wrong. If it's not too much trouble, I'd love to see what the patch would look like so I can see what I was doing wrong. Basically, I had originally set to auto-propagate the constants, and then ran the timing report and manually added paths that were unconstrained originally. But maybe I did it wrong in the first place...

enjoy-digital commented 4 years ago

That's sometimes indeed a bit tricky to get constraints correctly applied by Vivado. I'll prepare a PR for that.

bunnie commented 4 years ago

btw, i'm redo-ing the constraints heavily right now on a branch, so don't work on this. I think I actually found a bunch of areas where i'm doing the constraints wrong and cleaning them up.

enjoy-digital commented 4 years ago

ok thanks, i could still have a look when you will be done with your changes.

bunnie commented 4 years ago

sure, i'll drop a note here again once i get to that point. I'm refactoring a major interface to run at a much higher speed right now which is why i'm opening up the whole timing issue again...might take me a couple weeks.

enjoy-digital commented 4 years ago

As discussed with @bunnie, the main constraints are derivated automatically by Vivado and most of the manual constraints are here to ensure that the FPGA peripherals are correctly designed to meet timings (use of FPGA primitives, registers in the IOs, etc...). So they were useful during the development, are not really needed now (@bunnie verified the design was working without them) but are part for the design methology and timing non-regression checks should be kept.