sw: add 'uart_tx_timer_irq' example (with UART). - Githubissues

bieganski / mtkcpu

RISC-V CPU implementation in Amaranth HDL (aka nMigen)

GNU General Public License v2.0

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sw: add 'uart_tx_timer_irq' example (with UART). #76

Open bieganski opened 2 months ago